PIC16LF18854 Datasheet, PDF (427/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
29.5 Operation Examples
Unless otherwise specified, the following notes apply to
the following timing diagrams:
- Both the prescaler and postscaler are set to
1:1 (both the CKPS and OUTPS bits in the
TxCON register are cleared).
- The diagrams illustrate any clock except
Fosc/4 and show clock-sync delays of at
least two full cycles for both ON and
Timer2_ers. When using Fosc/4, the
clock-sync delay is at least one instruction
period for Timer2_ers; ON applies in the next
instruction period.
- The PWM Duty Cycle and PWM output are
illustrated assuming that the timer is used for
the PWM function of the CCP module as
described in Section 30.0 “Capture/Com-
pare/PWM Modules”. The signals are not a
part of the Timer2 module.
29.5.1 SOFTWARE GATE MODE
This mode corresponds to legacy Timer2 operation.
The timer increments with each clock input when
ON = 1 and does not increment when ON = 0. When
the TMRx count equals the PRx period count the timer
resets on the next clock and continues counting from 0.
Operation with the ON bit software controlled is illus-
trated in Figure 29-4. With PRx = 5, the counter
advances until TMRx = 5, and goes to zero with the
next clock.
FIGURE 29-4:
SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000)
Rev. 10-000195B
5/30/2014
MODE
0b00000
TMRx_clk
Instruction⁽¹⁾
BSF
BCF
BSF
ON
PRx
5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1
2
34501
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 427