PIC16LF18854 Datasheet, PDF (357/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
23.6 Register Definitions: ADC Control
REGISTER 23-1: ADCON0: ADC CONTROL REGISTER 0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
ADON
ADCONT
—
ADCS
—
bit 7
R/W-0/0
ADFRM0
U-0
R/W/HC-0
—
ADGO
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled
bit 6
ADCONT: ADC Continuous Operation Enable bit
1 = ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is
set) or until ADGO is cleared (regardless of the value of ADSOI)
0 = ADGO is cleared upon completion of each conversion trigger
bit 5
Unimplemented: Read as ‘0’
bit 4
ADCS: ADC Clock Selection bit
1 = Clock supplied from FRC dedicated oscillator
0 = Clock supplied by FOSC, divided according to ADCLK register
bit 3
Unimplemented: Read as ‘0’
bit 2
ADFRM0: ADC results Format/alignment Selection
1 = ADRES and ADPREV data are right-justified
0 = ADRES and ADPREV data are left-justified, zero-filled
bit 1
Unimplemented: Read as ‘0’
bit 0
ADGO: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is
cleared by hardware as determined by the ADCONT bit
0 = ADC conversion completed/not in progress
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 357