PIC16LF18854 Datasheet, PDF (64/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-13: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 13
CPU CORE REGISTERS; see Table 3-2 for specifics
68Ch
CWG3CLKCON
—
—
—
—
—
—
—
68Dh
CWG3ISM
—
—
—
—
IS<3:0>
68Eh
CWG3DBR
—
—
DBR<5:0>
68Fh
CWG3DBF
—
—
DBF<5:0>
690h
CWG3CON0
EN
LD
—
—
—
MODE<2:0>
691h
CWG3CON1
—
—
IN
—
POLD
POLC
POLB
692h
CWG3AS0
SHUTDOWN
REN
LSBD<1:0>
LSAC<1:0>
—
693h
CWG3AS1
—
AS6E
AS5E
AS4E
AS3E
AS2E
AS1E
694h
CWG3STR
OVRD
OVRC
OVRB
OVRA
STRD
STRC
STRB
695h
—
—
Unimplemented
696h
—
—
Unimplemented
697h
—
—
Unimplemented
698h
—
—
Unimplemented
699h
—
—
Unimplemented
69Ah
—
—
Unimplemented
69Bh
—
—
Unimplemented
69Ch
—
—
Unimplemented
69Dh
—
—
Unimplemented
69Eh
—
—
Unimplemented
69Fh
—
—
Unimplemented
Legend:
Note 1:
2:
x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Register present on PIC16F18855/75 devices only.
Unimplemented, read as ‘1’.
CS
POLA
—
AS0E
STRA
Value on:
POR, BOR
Value on all
other Resets
---- ---0
---- 0000
--00 0000
--00 0000
00-- -000
--x- 0000
0001 01--
-000 0000
0000 0000
—
—
—
—
—
—
—
—
—
—
—
---- ---0
---- 0000
--00 0000
--00 0000
00-- -000
--u- 0000
0001 01--
-000 0000
0000 0000
—
—
—
—
—
—
—
—
—
—
—