PIC16LF18854 Datasheet, PDF (116/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
Changing the clock post-divider without changing the
clock source (i.e., changing FOSC from 1 MHz to 2
MHz) is handled in the same manner as a clock source
change, as described previously. The clock source will
already be active, so the switch is relatively quick.
CSWHOLD must be clear (CSWHOLD = 0) for the
switch to complete.
The current COSC and CDIV are indicated in the
OSCCON2 register up to the moment when the switch
actually occurs, at which time OSCCON2 is updated
and ORDY is set. NOSCR is cleared by hardware to
indicate that the switch is complete.
6.3.2 PLL INPUT SWITCH
Switching between the PLL and any non-PLL source is
managed as described above. The input to the PLL is
established when NOSC selects the PLL, and main-
tained by the COSC setting.
When NOSC and COSC select the PLL with different
input sources, the system continues to run using the
COSC setting, and the new source is enabled per
NOSC. When the new oscillator is ready (and
CSWHOLD = 0), system operation is suspended while
the PLL input is switched and the PLL acquires lock.
6.3.3 CLOCK SWITCH AND SLEEP
If OSCCON1 is written with a new value and the device
is put to Sleep before the switch completes, the switch
will not take place and the device will enter Sleep
mode.
When the device wakes from Sleep and the
CSWHOLD bit is clear, the device will wake with the
‘new’ clock active, and the clock switch interrupt flag bit
(CSWIF) will be set.
When the device wakes from Sleep and the
CSWHOLD bit is set, the device will wake with the ‘old’
clock active and the new clock will be requested again.
Note: If the PLL fails to lock, the FSCM will
trigger.
FIGURE 6-6:
CLOCK SWITCH (CSWHOLD = 0)
OSCCON1
WRITTEN
OSC #1
OSC #2
ORDY
NOSCR
NOTE 2
CSWIF
NOTE 1
CSWHOLD
USER
CLEAR
Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.
DS40001824A-page 116
Preliminary
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