PIC16LF18854 Datasheet, PDF (592/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 36-3: PIC16(L)F18855/75 INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
14-Bit Opcode
Cycles
MSb
LSb
Status
Affected
Notes
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
MOVWI
Note 1:
2:
3:
CONTROL OPERATIONS
k
Relative Branch
–
Relative Branch with W
k
Call Subroutine
–
Call Subroutine with W
k
Go to address
k
Return from interrupt
k
Return with literal in W
–
Return from Subroutine
2
11 001k kkkk kkkk
2
00 0000 0000 1011
2
10 0kkk kkkk kkkk
2
00 0000 0000 1010
2
10 1kkk kkkk kkkk
2
00 0000 0000 1001
2
11 0100 kkkk kkkk
2
00 0000 0000 1000
INHERENT OPERATIONS
–
Clear Watchdog Timer
–
No Operation
–
Load OPTION_REG register with W
–
Software device Reset
–
Go into Standby or IDLE mode
f
Load TRIS register with W
1
00 0000 0110 0100 TO, PD
1
00 0000 0000 0000
1
00 0000 0110 0010
1
00 0000 0000 0001
1
00 0000 0110 0011 TO, PD
1
00 0000 0110 0fff
C-COMPILER OPTIMIZED
n, k
Add Literal k to FSRn
1
11 0001 0nkk kkkk
n mm
Move Indirect FSRn to W with pre/post inc/dec 1
00 0000 0001 0nmm Z
2, 3
modifier, mm
k[n]
Move INDFn to W, Indexed Indirect.
1
11 1111 0nkk kkkk Z
2
n mm
Move W to Indirect FSRn with pre/post inc/dec 1
00 0000 0001 1nmm
2, 3
modifier, mm
k[n]
Move W to INDFn, Indexed Indirect.
1
11 1111 1nkk kkkk
2
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
See Table in the MOVIW and MOVWI instruction descriptions.
DS40001824A-page 592
Preliminary
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