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PIC16LF18854 Datasheet, PDF (602/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture | |||
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PIC16(L)F18856/76
SWAPF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ï£ f ï£ 127
d ï [0,1]
(f<3:0>) ï® (destination<7:4>),
(f<7:4>) ï® (destination<3:0>)
None
The upper and lower nibbles of
register âfâ are exchanged. If âdâ is â0â,
the result is placed in the W register. If
âdâ is â1â, the result is placed in register
âfâ.
TRIS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Load TRIS Register with W
[ label ] TRIS f
5ï£fï£7
(W) ï® TRIS register âfâ
None
Move data from W register to TRIS
register.
When âfâ = 5, TRISA is loaded.
When âfâ = 6, TRISB is loaded.
When âfâ = 7, TRISC is loaded.
XORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
Exclusive OR literal with W
[ label ] XORLW k
0 ï£ï k ï£ï 255
(W) .XOR. k ï®ï ï¨W)
Z
The contents of the W register are
XORâed with the 8-bit literal âkâ. The
result is placed in the W register.
XORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Exclusive OR W with f
[ label ] XORWF f,d
0 ï£ f ï£ 127
d ï [0,1]
(W) .XOR. (f) ï®ï ï¨destination)
Z
Exclusive OR the contents of the W
register with register âfâ. If âdâ is â0â, the
result is stored in the W register. If âdâ
is â1â, the result is stored back in
register âfâ.
DS40001824A-page 602
Preliminary
ï£ 2016 Microchip Technology Inc.
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