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PIC16LF18854 Datasheet, PDF (629/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture | |||
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PIC16(L)F18856/76
TABLE 37-23: SPI MODE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol
Characteristic
Min.
Typâ Max. Units
Conditions
SP70* TSSL2SCH,
TSSL2SCL
SSï¯ to SCKï¯ or SCKï input
2.25*TCY
â
â ns
SP71* TSCH
SCK input high time (Slave mode)
TCY + 20
â
â ns
SP72* TSCL
SCK input low time (Slave mode)
TCY + 20
â
â ns
SP73* TDIV2SCH,
TDIV2SCL
Setup time of SDI data input to SCK
edge
100
â
â ns
SP74* TSCH2DIL, Hold time of SDI data input to SCK edge
100
TSCL2DIL
â
â ns
SP75* TDOR
SDO data output rise time
â
10
25 ns 3.0V ï£ VDD ï£ 5.5V
â
25
50 ns 1.8V ï£ VDD ï£ 5.5V
SP76* TDOF
SDO data output fall time
â
10
25 ns
SP77* TSSH2DOZ SSï to SDO output high-impedance
10
â
50 ns
SP78* TSCR
SCK output rise time
(Master mode)
â
10
25 ns 3.0V ï£ VDD ï£ 5.5V
â
25
50 ns 1.8V ï£ VDD ï£ 5.5V
SP79* TSCF
SCK output fall time (Master mode)
â
10
25 ns
SP80* TSCH2DOV, SDO data output valid after SCK edge
â
â
50 ns 3.0V ï£ VDD ï£ 5.5V
TSCL2DOV
â
â 145 ns 1.8V ï£ VDD ï£ 5.5V
SP81* TDOV2SCH, SDO data output setup to SCK edge
TDOV2SCL
1 Tcy
â
â ns
SP82* TSSL2DOV SDO data output valid after SSï¯ edge
â
â
50 ns
SP83* TSCH2SSH,
TSCL2SSH
SS ïï after SCK edge
1.5 TCY + 40
â
â ns
* These parameters are characterized but not tested.
â Data in âTypâ column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
ï£ 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 629
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