PIC16LF18854 Datasheet, PDF (611/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 37-5: MEMORY PROGRAMMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
High Voltage Entry Programming Mode Specifications
MEM01 V_IHH Voltage on MCLR/VPP pin to enter
programming mode
MEM02 I_PPGM Current on MCLR/VPP pin during
programming mode
Programming Mode Specifications
MEM10 V_BE
MEM11 I_DDPGM
VDD for Bulk Erase
Supply Current during Programming
operation
Data EEPROM Memory Specifications
MEM20 E_D
DataEE Byte Endurance
MEM21 T_{D_RET} Characteristic Retention
Min.
8
—
—
—
100k
—
MEM22 N_{D_REF} Total Erase/Write Cycles before
Refresh
MEM23 V_{D_RW} VDD for Read or Erase/Write
operation
MEM24 T_{D_BEW} Byte Erase and Write Cycle Time
Program Flash Memory Specifications
MEM30 E_P
Flash Memory Cell Endurance
—
VDDMIN
—
10k
MEM32 T_{P_RET} Characteristic Retention
—
Typ† Max. Units
Conditions
—
9
V _{(Note 2, Note 3)}
1
—
mA (Note 2)
2.7
—
V
—
10
mA
—
—
E/W -40C  TA  +85C
40
—
Year Provided no other
specifications are violated
—
100k E/W
—
VDDMAX
V
4.0
5.0
ms
—
—
E/W -40C  TA  +85C
(Note 1)
40
—
Year Provided no other
specifications are violated
MEM33 V_{P_RD} VDD for Read operation
VDDMIN
—
VDDMAX V
MEM34 V_{P_REW} VDD for Row Erase or Write
operation
VDDMIN
—
VDDMAX V
MEM35 T_{P_REW} Self-Timed Row Erase or Self-Timed —
Write
2.0
2.5
ms
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed
Write.
2: Required only if CONFIG4, bit LVP is disabled.
3: The MPLAB ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between
the ICD2 and target system when programming or debugging with the ICD2.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 611