PIC16LF18854 Datasheet, PDF (12/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18876) (CONTINUED)
RC0 15 30 34 32 ANC0
—
—
RC1 16 31 35 35 ANC1
—
—
RC2 17 32 36 36 ANC2
—
—
RC3 18 33 37 37 ANC3
—
—
RC4 23 38 42 42 ANC4
—
—
RC5 24 39 43 43 ANC5
—
—
RC6 25 40 44 44 ANC6
—
—
RC7 26 1 1 1
ANC7
—
—
RD0 19 34 38 38 AND0
—
—
—
—
—
—
—
—
—
—
—
T1CKI⁽¹⁾
—
—
T3CKI⁽¹⁾
T3G⁽¹⁾
SMTWIN1⁽¹⁾
—
SMTSIG1⁽¹⁾ CCP2⁽¹⁾
—
—
—
—
—
—
T5CKI⁽¹⁾
CCP1⁽¹⁾
—
—
— SCL1^(3,4) —
—
T2IN⁽¹⁾
—
—
SCK1⁽¹⁾
—
— SDA1^(3,4) —
—
—
—
—
SDI1⁽¹⁾
—
—
—
—
—
T4IN⁽¹⁾
—
—
—
—
—
CK⁽³⁾
—
—
—
—
—
—
—
RX⁽¹⁾
—
—
—
—
DT⁽³⁾
—
—
—
—
—
—
—
—
—
— — IOCC0 SOSCO
—
— — IOCC1 SOSCI
—
— — IOCC2
—
—
— — IOCC3
—
—
— — IOCC4
—
—
— — IOCC5
—
—
— — IOCC6
—
—
— — IOCC7
—
—
——
—
—
RD1 20 35 39 39 AND1
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RD2 21 36 40 40 AND2
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RD3 22 37 41 41 AND3
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RD4 27 2 2 2
AND4
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RD5 28 3 3 3
AND5
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RD6 29 4 4 4
AND6
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RD7 30 5 5 5
AND7
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RE0 8 23 25 25 ANE0
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RE1 9 24 26 26 ANE1
—
—
—
—
—
—
—
—
—
—
—
——
—
—
RE2 10 25 27 27 ANE2
—
—
—
—
—
—
—
—
—
—
—
——
—
—
Note 1:
2:
3:
4:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 13-1 for details on which port pins may be
used for this signal.
All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 13-3.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I²C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I²C specific or SMbus input buffer thresholds.