PIC16LF18854 Datasheet, PDF (556/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
FIGURE 33-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
OERR
RCIDL
RXPPS⁽¹⁾
RX/DT pin
PPS
Pin Buffer
and Control
Data
Recovery
MSb
Stop (8)
RSR Register
7 ••• 1
LSb
0 Start
Baud Rate Generator
BRG16
+1
SPxBRGH SPxBRGL
FOSC
÷n
Multiplier x4 x16 x64 ⁿ
SYNC 1 X 0 0 0
BRGH X 1 1 0 0
BRG16 X 1 0 1 0
FERR
Note 1: In Synchronous mode the DT output and RX input PPS
selections should enable the same pin.
RX9
RX9D
RCxREG Register
FIFO
8
Data Bus
RCIF
RCIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TX1STA)
• Receive Status and Control (RC1STA)
• Baud Rate Control (BAUD1CON)
These registers are detailed in Register 33-1,
Register 33-2 and Register 33-3, respectively.
The RX input pin is selected with the RXPPS. The CK
input is selected with the TXPPS register. TX, CK, and
DT output pins are selected with each pin’s RxyPPS
register. Since the RX input is coupled with the DT output
in Synchronous mode, it is the user’s responsibility to
select the same pin for both of these functions when
operating in Synchronous mode. The EUSART control
logic will control the data direction drivers automatically.
DS40001824A-page 556
Preliminary
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