PIC16LF18854 Datasheet, PDF (8/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIN ALLOCATION TABLES
TABLE 2: 28-PIN ALLOCATION TABLE (PIC16(L)F18856)
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RB0
RB1
RB2
RB3
RB4
Note
2 27 ANA0
—
—
C1IN0- —
—
—
—
—
—
—
CLCIN0⁽¹⁾ —
— IOCA0
—
C2IN0-
3 28 ANA1
—
—
C1IN1- —
—
—
—
—
—
—
CLCIN1⁽¹⁾ —
— IOCA1
—
C2IN1-
41
ANA2
VREF- DAC1OUT1 C1IN0+ —
—
—
—
—
C2IN0+
52
ANA3
VREF+
—
C1IN1+ —
—
—
MDCARL⁽¹⁾
—
—
—
—
—
— IOCA2
—
—
—
—
—
— IOCA3
—
63
ANA4
—
—
—
—
—
—
MDCARH⁽¹⁾
T0CKI⁽¹⁾
CCP5⁽¹⁾
—
—
—
— IOCA4
—
74
ANA5
—
—
—
—
SS1⁽¹⁾
—
MDSRC⁽¹⁾
—
—
—
—
—
— IOCA5
—
10 7
ANA6
—
—
—
—
—
—
—
—
—
—
—
—
— IOCA6 OSC2
CLKOUT
96
ANA7
—
21 18 ANB0
—
22 19 ANB1
—
23 20 ANB2
—
—
—
—
—
—
—
—
C2IN1+ ZCD
SS2⁽¹⁾
—
—
—
C1IN3-
—
SCL2^(3,4)
—
—
C2IN3-
SCK2⁽¹⁾
—
—
—
SDA2^(3,4)
—
—
SDI2⁽¹⁾
—
—
—
—
—
— IOCA7 OSC1
CLKIN
—
CCP4⁽¹⁾ CWG1IN⁽¹⁾
—
—
—
INT⁽¹⁾
—
IOCB0
—
—
CWG2IN⁽¹⁾
—
—
— IOCB1
—
—
—
CWG3IN⁽¹⁾
—
—
— IOCB2
—
24 21 ANB3
—
—
C1IN2- —
—
—
—
—
—
—
—
—
— IOCB3
—
C2IN2-
25 22 ANB4
—
—
—
—
—
—
—
T5G⁽¹⁾
—
—
—
—
— IOCB4
—
ADCACT⁽¹⁾
SMTWIN2⁽¹⁾
1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTX pins. Refer to Table 13-1 for details on which port pins may be
used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTX pin options as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
4: These pins are configured for I²C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I²C specific or SMbus input buffer thresholds.