PIC16LF18854 Datasheet, PDF (197/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 11-16: SCANTRIG: SCAN TRIGGER SELECTION REGISTER
U-0
—
bit 7
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
TSEL<3:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
TSEL<3:0>: Scanner Data Trigger Input Selection bits
1111-1010 = Reserved
1001 = SMT2_Match
1000 = SMT1_Match
0111 = TMR5_Overflow
0110 = TMR4_postscaled
0101 = TMR3_Overflow
0100 = TMR2_postscaled
0011 = TMR1_Overflow
0010 = TMR0_Overflow
0001 = CLKR
0000 = LFINTOSC
TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH CRC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
CRCACCH
ACC<15:8>
192
CRCACCL
ACC<7:0>
192
CRCCON0
EN
CRCGO
BUSY
ACCM
—
—
SHIFTM
FULL
191
CRCCON1
DLEN<3:0>
PLEN<3:0>
191
CRCDATH
DAT<15:8>
192
CRCDATL
DAT<7:0>
192
CRCSHIFTH
SHIFT<15:8>
193
CRCSHIFTL
SHIFT<7:0>
193
CRCXORH
XOR<15:8>
193
CRCXORL
XOR<7:1>
—
193
INTCON
GIE
PEIE
—
—
—
—
—
INTEDG 132
PIE4
—
—
TMR6IE
TMR5IE TMR4IE TMR3IE
TMR2IE TMR1IE 137
PIR4
—
—
TMR6IF
TMR5IF TMR4IF TMR3IF
TMR2IF TMR1IF 146
SCANCON0
EN SCANGO
BUSY
INVALID INTM
—
MODE<1:0>
194
SCANHADRH
HADR<15:8>
196
SCANHADRL
HADR<7:0>
196
SCANLADRH
LADR<15:8>
195
SCANLADRL
LADR<7:0>
195
SCANTRIG
—
—
—
—
TSEL<3:0>
197
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the CRC module.
* Page provides register information.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 197