PIC16LF18854 Datasheet, PDF (136/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-5: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
bit 7
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
RCIE
TXIE
BCL2IE
SSP2IE
R/W-0/0
BCL1IE
R/W-0/0
SSP1IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Enables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
BCL2IE: MSSP2 Bus Collision Interrupt Enable bit
1 = MSSP bus Collision interrupt enabled
0 = MSSP bus Collision interrupt disabled
SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit
1 = MSSP bus collision Interrupt
0 = Disables the MSSP Interrupt
BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1 = MSSP bus collision interrupt enabled
0 = MSSP bus collision interrupt disabled
SSP1IE: Synchronous Serial Port (MSSP1) Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt
controlled by PIE1-PIE8.
DS40001824A-page 136
Preliminary
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