PIC16LF18854 Datasheet, PDF (50/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-13: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other Resets
Bank 0
CPU CORE REGISTERS; see Table 3-2 for specifics
00Ch
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
00Dh
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
00Eh
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
00Fh
PORTD
X—
Unimplemented
—X
RD7
RD6
RD5
RD4
RD3
RD2
RD1
010h
PORTE
X—
—
—
—
—
RE3
—
—
—X
—
—
—
—
RE3
RE2
RE1
011h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
012h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
013h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
014h
TRISD
X—
Unimplemented
— X TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
015h
TRISE
X—
Unimplemented
—X
—
—
—
—
—
TRISE2
TRISE1
016h
LATA
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
017h
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
018h
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
019h
LATD
X—
Unimplemented
—X
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
01Ah
LATE
X-
Unimplemented
—X
—
—
—
—
—
LATE2
LATE1
Legend:
Note 1:
2:
x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Register present on PIC16F18855/75 devices only.
Unimplemented, read as ‘1’.
RA0
RB0
RC0
RD0
—
RE0
TRISA0
TRISB0
TRISC0
TRISD0
TRISE0
LATA0
LATB0
LATC0
LATD0
LATE0
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- ----
xxxx xxxx
---- x---
---- xxxx
1111 1111
1111 1111
1111 1111
---- ----
1111 1111
---- ----
---- -111
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- ----
xxxx xxxx
---- ----
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- ----
xxxx xxxx
---- x---
---- xxxx
1111 1111
1111 1111
1111 1111
---- ----
1111 1111
---- ----
---- -111
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ----
uuuu uuuu
---- ----
---- -uuu