PIC16LF18854 Datasheet, PDF (184/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 10-5: NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER
U-0
R/W-0/0
R/W-0/0
R/W/HC-0/0 R/W/HC-x/q
R/W-0/0
R/S/HC-0/0
—
NVMREGS
LWLO
FREE
WRERR^(1,2,3)
WREN
WR^(4,5,6)
bit 7
R/S/HC-0/0
RD⁽⁷⁾
bit 0
Legend:
R = Readable bit
S = Bit can only be set
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
4:
5:
6:
7:
Unimplemented: Read as ‘0’
NVMREGS: Configuration Select bit
1 = Access EEPROM, Configuration, User ID and Device ID Registers
0 = Access PFM
LWLO: Load Write Latches Only bit
When FREE = 0:
1 = The next WR command updates the write latch for this word within the row; no memory operation is initiated.
0 = The next WR command writes data or erases
Otherwise: The bit is ignored
FREE: PFM Erase Enable bit
When NVMREGS:NVMADR points to a PFM location:
1 = Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated
address is erased (to all 1s) to prepare for writing.
0 = All write operations have completed normally
WRERR: Program/Erase Error Flag bit^(1,2,3)
This bit is normally set by hardware.
1 = A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one while
NVMADR points to a write-protected address.
0 = The program or erase operation completed normally
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
WR: Write Control bit^(4,5,6)
When NVMREG:NVMADR points to a EEPROM location:
1 = Initiates an erase/program cycle at the corresponding EEPROM location
0 = NVM program/erase operation is complete and inactive
When NVMREG:NVMADR points to a PFM location:
1 = Initiates the operation indicated by Table 10-4
0 = NVM program/erase operation is complete and inactive
Otherwise: This bit is ignored
RD: Read Control bit⁽⁷⁾
1 = Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction cycle and the
bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.
0 = NVM read operation is complete and inactive
Bit is undefined while WR = 1 (during the EEPROM write operation it may be ‘0’ or ‘1’).
Bit must be cleared by software; hardware will not clear this bit.
Bit may be written to ‘1’ by software in order to implement test sequences.
This bit can only be set by following the unlock sequence of Section 10.4.2 “NVM Unlock Sequence”.
Operations are self-timed, and the WR bit is cleared by hardware when complete.
Once a write operation is initiated, setting this bit to zero will have no effect.
Reading from EEPROM loads only NVMDATL<7:0> (Register 10-1).
DS40001824A-page 184
Preliminary
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