PIC16LF18854 Datasheet, PDF (359/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 23-3: ADCON2: ADC CONTROL REGISTER 2
R/W-0/0
ADPSIS
bit 7
R/W-0/0
R/W-0/0
ADCRS<2:0>
R/W-0/0
R/W/HC-0
ADACLR
R/W-0/0
R/W-0/0
ADMD<2:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-4
bit 3
bit 2-0
ADPSIS: ADC Previous Sample Input Select bits
1 = ADRES is transferred to ADPREV at start-of-conversion
0 = ADFLTR is transferred to ADPREV at start-of-conversion
ADCRS<2:0>: ADC Accumulated Calculation Right Shift Select bits
111 = Reserved
110 = Reserved
101 through 000:
If ADMD = 100:
Low-pass filter time constant is 2^ADCRS, filter gain is 1:1
If ADMD = 001, 010 or 011:
The accumulated value is right-shifted by ADCRS (divided by 2^ADCRS)⁽²⁾
Otherwise:
Bits are ignored
ADACLR: ADC Accumulator Clear Command bit
1 = Initial clear of ADACC, ADAOV, and the sample counter. Bit is cleared by hardware.
0 = Clearing action is complete (or not started)
ADMD<2:0>: ADC Operating Mode Selection bits⁽¹⁾
111 = Reserved
•
•
•
101 = Reserved
100 = Low-pass Filter mode
011 = Burst Average mode
010 = Average mode
001 = Accumulate mode
000 = Basic (Legacy) mode
Note 1: See Table 23-3 for Full mode descriptions.
2: All results of divisions using the ADCRS bits are truncated, not rounded.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 359