PIC16LF18854 Datasheet, PDF (384/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 24-6: NCO1INCL: NCO1 INCREMENT REGISTER – LOW BYTE^(1,2)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1INC<7:0>
bit 7
R/W-1/1
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
NCO1INC<7:0>: NCO1 Increment, Low Byte
Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
2: DDSINC is double-buffered as INCBUF; INCBUF is updated on the next falling edge of NCOCLK after
writing to NCO1INCL; NCO1INCU and NCO1INCH should be written prior to writing NCO1INCL.
REGISTER 24-7: NCO1INCH: NCO1 INCREMENT REGISTER – HIGH BYTE⁽¹⁾
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCO1INC<15:8>
bit 7
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
NCO1INC<15:8>: NCO1 Increment, High Byte
Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
REGISTER 24-8: NCO1INCU: NCO1 INCREMENT REGISTER – UPPER BYTE⁽¹⁾
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
—
NCO1INC<19:16>
bit 7
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
NCO1INC<19:16>: NCO1 Increment, Upper Byte
Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.
DS40001824A-page 384
Preliminary
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