PIC16LF18854 Datasheet, PDF (175/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

FIGURE 10-4:
BLOCK WRITES TO PROGRAM FLASH MEMORY (PFM) WITH 32 WRITE LATCHES
76
07
NVMADRH
43
0
NVMADRL
- rA r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c3 c2 c1 c0
7
5
07
0
- - _NVMDATH
NVMDATL
6
8
Rev. 10-000004E
8/14/2015
14
Program Memory Write Latches
11
4
14
14
14
14
NVMADRL<3:0>
Write Latch #0 Write Latch #1
00h
01h
14
14
Write Latch #30 Write Latch #31
1Eh
1Fh
14
14
NVMREGS=0
Row
000h
001h
002h
Addr
0000h
0010h
0020h
Addr
0001h
0011h
0021h
Addr
001Eh
003Eh
005Eh
Addr
001Fh
003Fh
005Fh
NVMADRH<6:0>
NVMADRL<7:4>
Row
Address
Decode
1FEh
1FFh
1FE0h
1FF0h
1FE1h
1FF1h
1FDEh
1FFEh
Flash Program Memory
1FDFh
1FFFh
NVMREGS = 1
800h 8000h - 8003h 8004h 8005h 8006h 8007h – 800Bh
USER ID 0 - 3
reserved
MASK/
REV ID
DEVICE ID
Configuration
Words
Configuration Memory
800Ch - 801Fh
reserved