PIC16LF18854 Datasheet, PDF (492/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
31.6.5 I²C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition (Figure 31-27) occurs when
the RSEN bit of the SSPxCON2 register is pro-
grammed high and the master state machine is no lon-
ger active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the
Baud Rate Generator is loaded and begins counting.
The SDA pin is released (brought high) for one Baud
Rate Generator count (TBRG). When the Baud Rate
Generator times out, if SDA is sampled high, the SCL
pin will be deasserted (brought high). When SCL is
sampled high, the Baud Rate Generator is reloaded
and begins counting. SDA and SCL must be sampled
high for one TBRG. This action is then followed by
assertion of the SDA pin (SDA = 0) for one TBRG while
SCL is high. SCL is asserted low. Following this, the
RSEN bit of the SSPxCON2 register will be automati-
cally cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit of the SSPxSTAT register will be set. The
SSPxIF bit will not be set until the Baud Rate Generator
has timed out.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting
to transmit a data ‘1’.
FIGURE 31-27: REPEATED START CONDITION WAVEFORM
SDA
Write to SSPxCON2
occurs here
SDA = 1,
SCL (no change)
SDA = 1,
SCL = 1
TBRG TBRG TBRG
S bit set by hardware
At completion of Start bit,
hardware clears RSEN bit
and sets SSPxIF
1st bit
Write to SSPxBUF occurs here
TBRG
SCL
Sr
Repeated Start
TBRG
DS40001824A-page 492
Preliminary
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