S912XHZ512F1VAG Datasheet, PDF (98/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
When the SCI1 transmitter is enabled, the PP[0] pin becomes the TXD1 output pin and the associated Data
Direction Register bit has no effect. When the SCI1 receiver is enabled, the PP[2] pin becomes the RXD1
input pin and the associated Data Direction Register bit has no effect.
If the PWM, IIC0, IIC1 and SCI1 functions are disabled, the corresponding Data Direction Register bit
reverts to control the I/O direction of the associated pin.
Table 2-32. DDRP Field Descriptions
Field
7:0
Data Direction Port P
DDRP[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
2.3.9.4 Port P Reduced Drive Register (RDRP)
Module Base + 0x001B
7
R
RDRP7
W
6
RDRP6
5
RDRP5
4
RDRP4
3
RDRP3
2
RDRP2
1
RDRP1
0
RDRP0
Reset
0
0
0
0
0
0
0
0
Figure 2-45. Port P Reduced Drive Register (RDRP)
Read:Anytime. Write:Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 2-33. RDRP Field Descriptions
Field
Description
7:0
Reduced Drive Port P
RDRP[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12XHZ512 Data Sheet, Rev. 1.06
98
Freescale Semiconductor