S912XHZ512F1VAG Datasheet, PDF(738/978 Page) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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S912XHZ512F1VAG Datasheet, PDF (738/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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Chapter 20 Voltage Regulator (S12VREG3V3V5)

Table 20-10. Interrupt Vectors

Interrupt Source

Autonomous periodical interrupt (API)

Local Enable

APIE = 1

20.4.10.1 Low-Voltage Interrupt (LVI)

In FPM, VREG_3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA, the

status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when VDDA rises above level VLVID. An

interrupt, indicated by ï¬ag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable

bit LVIE = 1.

NOTE

On entering the reduced power mode, the LVIF is not cleared by the

VREG_3V3.

20.4.10.2 Autonomous Periodical Interrupt (API)

As soon as the conï¬gured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated

by ï¬ag APIF = 1, is triggered if interrupt enable bit APIE = 1.

MC9S12XHZ512 Data Sheet, Rev. 1.06

738

Freescale Semiconductor

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