S912XHZ512F1VAG Datasheet, PDF (523/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Module Base + 0x0006
Access: User read/write⁽¹⁾
7
6
5
4
3
2
R
0
0
0
0
0
TXE2
W
Reset:
0
0
0
0
0
1
= Unimplemented
Figure 14-10. MSCAN Transmitter Flag Register (CANTFLG)
1. Read: Anytime
Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored
1
TXE1
1
0
TXE0
1
NOTE
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
Table 14-13. CANTFLG Register Field Descriptions
Field
Description
2-0
TXE[2:0]
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a
transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 14.3.2.10, “MSCAN Transmitter
Message Abort Acknowledge Register (CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit
is cleared (see Section 14.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”).
When listen-mode is active (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx flags
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
14.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER)
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Module Base + 0x0007
Access: User read/write⁽¹⁾
R
W
Reset:
7
6
5
4
3
2
1
0
0
0
0
0
TXEIE2
TXEIE1
0
0
0
0
0
0
0
= Unimplemented
Figure 14-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
0
TXEIE0
0
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
523