S912XHZ512F1VAG Datasheet, PDF (337/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 7 Clocks and Reset Generator (S12CRGV6)
7.3.2.1 CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (f_SCM).
PLLCLK = 2xOSCCLKx₍---⁽_{R--S---E-Y---F--N--D--R---V---+--+---1--1--}⁾--₎
NOTE
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Module Base +0x_00
7
R
0
W
Reset
0
6
5
4
3
2
0
SYN5
SYN4
SYN3
SYN2
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-4. CRG Synthesizer Register (SYNR)
1
SYN1
0
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
0
SYN0
0
7.3.2.2 CRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
Module Base +0x_01
7
R
0
W
Reset
0
6
5
4
3
2
0
REFDV5 REFDV4 REFDV3 REFDV2
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-5. CRG Reference Divider Register (REFDV)
1
REFDV1
0
0
REFDV0
0
Read: Anytime
Write: Anytime except when PLLSEL = 1
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
337