S912XHZ512F1VAG Datasheet, PDF(558/978 Page) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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S912XHZ512F1VAG Datasheet, PDF (558/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

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Chapter 14 Freescaleâs Scalable Controller Area Network (S12MSCANV3)

14.4.5.7 Disabled Mode

The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving,

however the register map can still be accessed as speciï¬ed.

14.4.5.8 Programmable Wake-Up Function

The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity

is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0). The sensitivity to existing

CAN bus action can be modiï¬ed by applying a low-pass ï¬lter function to the RXCAN input line (see

control bit WUPM in Section 14.3.2.2, âMSCAN Control Register 1 (CANCTL1)â).

This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines.

Such glitches can result fromâfor exampleâelectromagnetic interference within noisy environments.

14.4.6 Reset Initialization

The reset state of each individual bit is listed in Section 14.3.2, âRegister Descriptions,â which details all

the registers and their bit-ï¬elds.

14.4.7 Interrupts

This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated

ï¬ags. Each interrupt is listed and described separately.

14.4.7.1 Description of Interrupt Operation

The MSCAN supports four interrupt vectors (see Table 14-39), any of which can be individually masked

(for details see Section 14.3.2.6, âMSCAN Receiver Interrupt Enable Register (CANRIER)â to

Section 14.3.2.8, âMSCAN Transmitter Interrupt Enable Register (CANTIER)â).

Refer to the device overview section to determine the dedicated interrupt vector addresses.

Table 14-39. Interrupt Vectors

Interrupt Source

Wake-Up Interrupt (WUPIF)

Error Interrupts Interrupt (CSCIF, OVRIF)

Receive Interrupt (RXF)

Transmit Interrupts (TXE[2:0])

CCR Mask

Local Enable

I bit

CANRIER (WUPIE)

I bit

CANRIER (CSCIE, OVRIE)

I bit

CANRIER (RXFIE)

I bit

CANTIER (TXEIE[2:0])

14.4.7.2 Transmit Interrupt

At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message

for transmission. The TXEx ï¬ag of the empty message buffer is set.

MC9S12XHZ512 Data Sheet, Rev. 1.06

558

Freescale Semiconductor

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