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| S912XHZ512F1VAG Datasheet, PDF (445/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
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Chapter 11 Motor Controller (MC10B12CV2) Block Description
VDDM
PWM Channel x
MnC0P
MnC0M
Released
PWM Output
PWM Channel x + 1
MnC1P
MnC1M
Released
PWM Output
VSSM
VDDM
Figure 11-11. Typical Quad Half H-Bridge Mode Conï¬guration
VSSM
11.4.1.2 Relationship Between PWM Mode and PWM Channel Enable
The pair of motor controller channels cannot be placed into dual full H-bridge mode unless both motor
controller channels have been enabled (MCAM[1:0] not equal to 00) and dual full H-bridge mode is
selected for both PWM channels (MCOM[1:0] = 11). If only one channel is set to dual full H-bridge mode,
this channel will operate in full H-bridge mode, the other as programmed.
11.4.1.3 Relationship Between Sign, Duty, Dither, RECIRC, Period,
and PWM Mode Functions
11.4.1.3.1 PWM Alignment Modes
Each PWM channel can be programmed individually to three different alignment modes. The mode is
determined by the MCAM[1:0] bits in the corresponding channel control register.
Left aligned (MCAM[1:0] = 01): The output will start active (low if RECIRC = 0 or high if RECIRC = 1)
and will turn inactive (high if RECIRC = 0 or low if RECIRC = 1) after the number of counts speciï¬ed by
the corresponding duty cycle register.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
445
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