S912XHZ512F1VAG Datasheet, PDF (72/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.2.3 Port C Data Direction Register (DDRC)
Module Base + 0x0055
R
W
Reset
7
DDRC7
0
6
DDRC6
5
DDRC5
4
DDRC4
3
DDRC3
2
DDRC2
0
0
0
0
0
Figure 2-8. Port C Data Direction Register (DDRC)
Read: Anytime. Write: Anytime.
This register configures port pins PC[7:0] as either input or output.
Table 2-5. DDRC Field Descriptions
Field
7:0
Data Direction Port C
DDRC[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
2.3.2.4 Port D Data Direction Register (DDRD)
Module Base + 0x0055
R
W
Reset
7
DDRD7
0
6
DDRD6
5
DDRD5
4
DDRD4
3
DDRD3
2
DDRD2
0
0
0
0
0
Figure 2-9. Port D Data Direction Register (DDRD)
Read: Anytime. Write: Anytime.
This register configures port pins PD[7:0] as either input or output.
Table 2-6. DDRD Field Descriptions
Field
7:0
Data Direction Port D
DDRD[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
1
DDRC1
0
1
DDRD1
0
0
DDRC0
0
0
DDRD0
0
MC9S12XHZ512 Data Sheet, Rev. 1.06
72
Freescale Semiconductor