S912XHZ512F1VAG Datasheet, PDF (735/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 20 Voltage Regulator (S12VREG3V3V5)
20.3.2.6 Reserved 06
The Reserved 06 is reserved for test purposes.
Module Base + 0x0006
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-8. Reserved 06
20.3.2.7 Reserved 07
The Reserved 07 is reserved for test purposes.
Module Base + 0x0007
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-9. Reserved 07
20.4 Functional Description
20.4.1 General
Module VREG_3V3 is a voltage regulator, as depicted in Figure 20-1. The regulator functional elements
are the regulator core (REG), a low-voltage detect module (LVD), a control block (CTRL), a power-on
reset module (POR), and a low-voltage reset module (LVR).
20.4.2 Regulator Core (REG)
Respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ
only in the amount of current that can be delivered.
The regulator is a linear regulator with a bandgap reference when operated in full peformance mode. It acts
as a voltage clamp in reduced power mode. All load currents flow from input V_DDR to V_SS or V_SSPLL. The
reference circuits are supplied by V_DDA and V_SSA.
20.4.2.1 Full Performance Mode
In full peformance mode, the output voltage is compared with a reference voltage by an operational
amplifier. The amplified input voltage difference drives the gate of an output transistor.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
735