S912XHZ512F1VAG Datasheet, PDF (55/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 1 MC9S12XHZ Family Device Overview
NOTE
If the MCU is secured the COP timeout rate is always set to the longest
period (CR[2:0] = 111) after COP reset.
Table 1-10. Initial COP Rate Configuration
NV[2:0] in
FCTL Register
000
001
010
011
100
101
110
111
CR[2:0] in
COPCTL Register
111
110
101
100
011
010
001
000
Table 1-11. Initial WCOP Configuration
NV[3] in
FCTL Register
1
0
WCOP in
COPCTL Register
0
1
1.8 ATD External Trigger Input Connection
The ATD_10B16C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and
ETRIG3. The external trigger feature allows the user to synchronize ATD conversion to external trigger
events. Table 1-12 shows the connection of the external trigger inputs on MC9S12XHZ Family.
Table 1-12. ATD External Trigger Sources
External Trigger
Input
ETRIG0
ETRIG1
ETRIG2
ETRIG3
Connectivity
Pulse width modulator channel 1
Pulse width modulator channel 3
Periodic interrupt timer hardware trigger 0
Periodic interrupt timer hardware trigger 1
Consult the ATD_10B16C block description chapter for information about the analog-to-digital converter
module.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
55