S912XHZ512F1VAG Datasheet, PDF (847/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 24 Interrupt (S12XINTV1)
Stacked IPL
0
0
4
0
0
0
IPL in CCR
Processing Levels
0
4
7
4
3
7
6
L7
RTI
5
4
3
2
L4
1
0
Reset
RTI
L3 (Pending)
L1 (Pending)
Figure 24-14. Interrupt Processing Example
1
RTI
0
RTI
24.5.3 Wake Up from Stop or Wait Mode
24.5.3.1 CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking
the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake
up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
• If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.
• An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCR.
• I bit maskable interrupt requests which are configured to be handled by the XGATE are not capable
of waking up the CPU.
An XIRQ request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set.
24.5.3.2 XGATE Wake Up from Stop or Wait Mode
Interrupt request channels which are configured to be handled by the XGATE are capable of waking up the
XGATE. Interrupt request channels handled by the XGATE do not affect the state of the CPU.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
847