S912XHZ512F1VAG Datasheet, PDF (602/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 16 Serial Peripheral Interface (S12SPIV4)
16.2.3 SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
16.2.4 SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
16.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
16.3.1 Module Memory Map
The memory map for the SPI is given in Figure 16-2. The address listed for each register is the sum of a
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
0x0000
R
SPICR1 _W ^SPIE
0x0001
R
0
SPICR2 _W
0x0002
R
0
SPIBR
W
0x0003
SPISR
R SPIF
W
0x0004
R
Reserved _W
0x0005
SPIDR
R
Bit 7
W
0x0006
R
Reserved _W
0x0007
R
Reserved _W
6
SPE
0
SPPR2
0
5
4
3
SPTIE
MSTR
CPOL
0
MODFEN BIDIROE
0
SPPR1
SPPR0
SPTEF
MODF
0
6
5
4
3
= Unimplemented or Reserved
Figure 16-2. SPI Register Summary
2
CPHA
0
SPR2
0
2
1
SSOE
SPISWAI
SPR1
0
1
Bit 0
LSBFE
SPC0
SPR0
0
Bit 0
MC9S12XHZ512 Data Sheet, Rev. 1.06
602
Freescale Semiconductor