S912XHZ512F1VAG Datasheet, PDF (694/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-19. PACTL Field Descriptions (continued)
Field
Description
4
PEDGE
3:2
CLK[1:0]
2
PAOVI
0
PAI
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1). Refer to Table 19-20.
For PAMOD bit = 0 (event counter mode).
0 Falling edges on IC7 pin cause the count to be incremented
1 Rising edges on IC7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 IC7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on IC7
sets the PAIF flag.
1 IC7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on IC7 sets
the PAIF flag.
If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the
timer prescaler.
Clock Select Bits — For the description of PACLK please refer to Figure 19-72.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input
clock to the timer counter. The change from one selected clock to the other happens immediately after these bits
are written. Refer to Table 19-21.
Pulse Accumulator A Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAOVF is set
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAIF is set
.
Table 19-20. Pin Action
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Pin Action
Falling edge
Rising edge
Divide by 64 clock enabled with pin high level
Divide by 64 clock enabled with pin low level
CLK1
0
0
1
1
Table 19-21. Clock Selection
CLK0
0
1
0
1
Clock Source
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
MC9S12XHZ512 Data Sheet, Rev. 1.06
694
Freescale Semiconductor