S912XHZ512F1VAG Datasheet, PDF (690/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 19.3.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 19.3.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 19-18. TFLG2 Field Descriptions
Field
7
TOF
Description
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000.
19.3.2.14 Timer Input Capture/Output Compare Registers 0–7
Module Base + 0x0010
R
W
Reset
15
Bit 15
0
14
Bit 14
0
13
Bit 13
0
12
Bit 12
0
11
Bit 11
0
10
Bit 10
0
9
Bit 9
0
8
Bit 8
0
Figure 19-20. Timer Input Capture/Output Compare Register 0 High (TC0)
Module Base + 0x0011
R
W
Reset
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
0
Bit 0
0
Figure 19-21. Timer Input Capture/Output Compare Register 0 Low (TC0)
Module Base + 0x0012
R
W
Reset
15
Bit 15
0
14
Bit 14
0
13
Bit 13
0
12
Bit 12
0
11
Bit 11
0
10
Bit 10
0
9
Bit 9
0
8
Bit 8
0
Figure 19-22. Timer Input Capture/Output Compare Register 1 High (TC1)
MC9S12XHZ512 Data Sheet, Rev. 1.06
690
Freescale Semiconductor