S912XHZ512F1VAG Datasheet, PDF (816/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 23 External Bus Interface (S12XEBIV3)
23.4 Functional Description
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
23.4.1 Operating Modes and External Bus Properties
A summary of the external bus interface functions for each operating mode is shown in Table 23-7.
Table 23-7. Summary of Functions
Properties
(if Enabled)
Single-Chip Modes
Normal
Special
Single-Chip Single-Chip
Normal
Expanded
Expanded Modes
Emulation
Single-Chip
Emulation
Expanded
Special
Test
PRR access¹
Internal access
visible externally
External
address access
and
unimplemented area
access²
Flash area
address access⁴
2 cycles
read internal
write internal
—
—
—
Bus signals
—
Data select signals
—
(if 16-bit data bus)
Data direction signals
—
—
Chip Selects
External wait
—
feature
Reduced input
—
threshold enabled on
1 _{Incl. S12X_EBI registers}
Timing Properties
2 cycles
read internal
write internal
2 cycles
read internal
write internal
—
—
2 cycles
read external
write int & ext
1 cycle
2 cycles
read external
write int & ext
1 cycle
2 cycles
read internal
write internal
1 cycle
—
Max. of 2 to 9
1 cycle
Max. of 2 to 9
1 cycle
programmed
programmed
cycles
cycles
or n cycles of
ext. wait³
or n cycles of
ext. wait³
—
—
1 cycle
1 cycle
1 cycle
Signal Properties
—
ADDR[22:1]
DATA[15:0]
—
UDS
LDS
—
RE
WE
—
CS0
CS1
CS2
CS3
—
EWAIT
ADDR[22:20]/A ADDR[22:20]/A
CC[2:0]
CC[2:0]
ADDR[19:16]/ ADDR[19:16]/
IQSTAT[3:0] IQSTAT[3:0]
ADDR[15:0]/ ADDR[15:0]/
IVD[15:0]
IVD[15:0]
DATA[15:0]
DATA[15:0]
ADDR0
LSTRB
ADDR0
LSTRB
RW
RW
—
CS0
CS1
CS2
CS3
—
EWAIT
ADDR[22:0]
DATA[15:0]
ADDR0
LSTRB
RW
CS0
CS1
CS2
CS3
—
—
Refer to
DATA[15:0]
DATA[15:0]
Refer to
Table 23-3
EWAIT
EWAIT
Table 23-3
MC9S12XHZ512 Data Sheet, Rev. 1.06
816
Freescale Semiconductor