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S912XHZ512F1VAG Datasheet, PDF (311/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
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TST
Test Register
Chapter 5 XGATE (S12XGATEV2)
TST
Operation
RS â 0 â NONE (translates to SUB R0, RS, R0)
Subtracts zero from the content of register RS using binary subtraction and discards the result.
CCR Effects
NZVC
ââââ
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overï¬ow resulted from the operation; cleared otherwise.
RS[15] & result[15]
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & result[15]
Code and CPU Cycles
Source Form
TST RS
Address
Mode
TRI
Machine Code
0 0 0 1 1 0 0 0 RS1
Cycles
00000
P
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
311
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