S912XHZ512F1VAG Datasheet, PDF (209/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 5
XGATE (S12XGATEV2)
Revision History
Version
Number
02.22
02.23
V03.24
Date
14 Dec
2005
19 Mar
2007
13 Feb
2009
Author
Description of Changes
Updated code example
Internal updates
- Minor corrections (5.3.1.4/5-220)
5.1 Introduction
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the
MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the
transferred data and perform complex communication protocols.
The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s
interrupt load.
Figure 5-1 gives an overview on the XGATE architecture.
This document describes the functionality of the XGATE module, including:
• XGATE registers (Section 5.3, “Memory Map and Register Definition”)
• XGATE RISC core (Section 5.4.1, “XGATE RISC Core”)
• Hardware semaphores (Section 5.4.4, “Semaphores”)
• Interrupt handling (Section 5.5, “Interrupts”)
• Debug features (Section 5.6, “Debug Mode”)
• Security (Section 5.7, “Security”)
• Instruction set (Section 5.8, “Instruction Set”)
5.1.1 Glossary of Terms
XGATE Request
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
209