S912XHZ512F1VAG Datasheet, PDF (484/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 13 Inter-Integrated Circuit (IICV3) Block Description
IBC5-3
(bin)
000
001
010
011
100
101
110
111
Table 13-4. I-Bus Tap and Prescale Values
IBC2-0
(bin)
000
001
010
011
100
101
110
111
SCL Tap
(clocks)
5
6
7
8
9
10
12
15
SDA Tap
(clocks)
1
1
2
2
3
3
4
4
Table 13-5. Prescale Divider Encoding
scl2start
(clocks)
2
2
2
6
14
30
62
126
scl2stop
(clocks)
7
7
9
9
17
33
65
129
scl2tap
(clocks)
4
4
6
6
14
30
62
126
tap2tap
(clocks)
1
2
4
8
16
32
64
128
Table 13-6. Multiplier Factor
IBC7-6
00
01
10
11
MUL
01
02
04
RESERVED
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 13-4, all subsequent tap points are separated by 2^IBC5-3 as shown in the
tap2tap column in Table 13-5. The SCL Tap is used to generated the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 13-6.
MC9S12XHZ512 Data Sheet, Rev. 1.06
484
Freescale Semiconductor