S912XHZ512F1VAG Datasheet, PDF (400/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description
9.3.2.12 ATD Input Enable Register 0 (ATDDIEN0)
Module Base + 0x000C
R
W
Reset
7
IEN15
0
6
IEN14
5
IEN13
4
IEN12
3
IEN11
2
IEN10
0
0
0
0
0
Figure 9-14. ATD Input Enable Register 0 (ATDDIEN0)
1
IEN9
0
0
IEN8
0
Read: Anytime
Write: anytime
Table 9-23. ATDDIEN0 Field Descriptions
Field
7:0
IEN[15:8]
Description
ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input
pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
9.3.2.13 ATD Input Enable Register 1 (ATDDIEN1)
Module Base + 0x000D
R
W
Reset
7
IEN7
0
Read: Anytime
Write: Anytime
6
IEN6
5
IEN5
4
IEN4
3
IEN3
2
IEN2
0
0
0
0
0
Figure 9-15. ATD Input Enable Register 1 (ATDDIEN1)
1
IEN1
0
0
IEN0
0
Field
7:0
IEN[7:0]
Table 9-24. ATDDIEN1 Field Descriptions
Description
ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input
pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
MC9S12XHZ512 Data Sheet, Rev. 1.06
400
Freescale Semiconductor