S912XHZ512F1VAG Datasheet, PDF (419/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 10 Liquid Crystal Display (LCD32F4BV1) Block Description
Read: anytime
Write: anytime
Table 10-6. LCD RAM Field Descriptions
Field
31:0
3:0
FP[31:0]
BP[3:0]
Description
LCD Segment ON — The FP[31:0]BP[3:0] bit displays (turns on) the LCD segment connected between FP[31:0]
and BP[3:0].
0 LCD segment OFF
1 LCD segment ON
10.4 Functional Description
This section provides a complete functional description of the LCD32F4BV1 block, detailing the
operation of the design from the end user perspective in a number of subsections.
10.4.1 LCD Driver Description
10.4.1.1 Frontplane, Backplane, and LCD System During Reset
During a reset the following conditions exist:
• The LCD32F4BV1 system is configured in the default mode, 1/4 duty and 1/3 bias, that means all
backplanes are used.
• All frontplane enable bits, FP[31:0]EN are cleared and the ON/OFF control for the display, the
LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state. The MCU pin state during reset is defined by the port integration module (PIM).
10.4.1.2 LCD Clock and Frame Frequency
The frequency of the oscillator clock (OSCCLK) and divider determine the LCD clock frequency. The
divider is set by the LCD clock prescaler bits, LCLK[2:0], in the LCD control register 0 (LCDCR0).
Table 10-7 shows the LCD clock and frame frequency for some multiplexed mode at OSCCLK = 16 MHz,
8 MHz, 4 MHz, 2 MHz, 1 MHz, and 0.5 MHz.
Table 10-7. LCD Clock and Frame Frequency
Oscillator
Frequency in
MHz
OSCCLK = 0.5
OSCCLK = 1.0
OSCCLK = 2.0
LCD Clock Prescaler
LCLK2 LCLK1 LCLK0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
Divider
LCD Clock
Frequency [Hz]
Frame Frequency [Hz]
1/1 Duty 1/2 Duty 1/3 Duty 1/4 Duty
1024
488
2048
244
2048
488
4096
244
4096
488
8192
244
488
244
163
122
244
122
81
61
488
244
163
122
244
122
81
61
488
244
163
122
244
122
81
61
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
419