S912XHZ512F1VAG Datasheet, PDF (821/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

23.4.2.4.3 Read-Write-Read Access Timing
Chapter 23 External Bus Interface (S12XEBIV3)
Table 23-16. Interleaved Read-Write-Read Accesses (1 Cycle)
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0] ...
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0] ...
DATA[15:0] (internal read) ...
DATA[15:0] (external read) ...
RW
...
Access #0
1
high
low
acc 0
addr 0 iqstat -1
?
?
z
?
z
1
1
Access #1
Access #2
2
3
...
high
low
high
low ...
acc 1
acc 2 ...
addr 1
iqstat 0
addr 2
iqstat 1 ...
ivd 0
x
...
z
(write) data 1
z
...
data 0
(write) data 1
z
...
0
0
1
1
...
23.4.3 Accesses to Port Replacement Registers
All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode.
If writing to these addresses in emulation modes, the access is directed to both, the internal register and
the external resource while reads will be treated external.
The XEBI control registers also belong to this category.
23.4.4 Stretched External Bus Accesses
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI
supports stretched external bus accesses (wait states).
This feature is available in normal expanded mode and emulation expanded mode for accesses to all
external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2
cycles, respectively.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
821