S912XHZ512F1VAG Datasheet, PDF (698/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 19 Enhanced Capture Timer (ECT16B8CV3)
Table 19-23. MCCTL Field Descriptions (continued)
Field
Description
4
ICLAT
Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3
and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse
accumulators will be automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will always return zero.
3
FLMC
Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus
down-counter is enabled (MCEN = 1).
A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets
the modulus counter prescaler.
Write zero to this bit has no effect. Read of this bit will return always zero.
2
MCEN
Modulus Down-Counter Enable
0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early
interrupt flag when the modulus down-counter is enabled.
1 Modulus counter is enabled.
1:0
Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler
MCPR[1:0] when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of
the load register into the modulus counter count register occurs.
Table 19-24. Modulus Counter Prescaler Select
MCPR1
0
0
1
1
MCPR0
0
1
0
1
Prescaler Division
1
4
8
16
19.3.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Module Base + 0x0027
R
W
Reset
7
6
5
4
3
2
1
0
0
0
POLF3
POLF2
POLF1
MCZF
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-43. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
0
POLF0
0
Read: Anytime
Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a
zero will not affect the current status of the bit.
MC9S12XHZ512 Data Sheet, Rev. 1.06
698
Freescale Semiconductor