S912XHZ512F1VAG Datasheet, PDF (108/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
2.3.11.2 Port T Input Register (PTIT)
Module Base + 0x0001
R
W
Reset
7
PTIT7
u
6
PTIT6
5
PTIT5
4
PTIT4
3
PTIT3
2
PTIT2
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 2-59. Port T Input Register (PTIT)
1
PTIT1
u
0
PTIT0
u
Read: Anytime. Write: Never, writes to this register have no effect.
If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled), a read
returns a 1.
If the LCD frontplane driver of the associated I/O pin is disabled (or LCD module is disabled), a read
returns the status of the associated pin.
2.3.11.3 Port T Data Direction Register (DDRT)
Module Base + 0x0002
R
W
Reset
7
DDRT7
0
6
DDRT6
5
DDRT5
4
DDRT4
3
DDRT3
2
DDRT2
0
0
0
0
0
Figure 2-60. Port T Data Direction Register (DDRT)
1
DDRT1
0
0
DDRT0
0
Read: Anytime. Write: Anytime.
This register configures port pins PT[7:0] as either input or output.
If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the
corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver
is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control
the I/O direction of the associated pin.
If the ECT module is enabled, each port pin configured for output compare is forced to be an output and
the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled,
the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
If the ECT module is enabled, each port pin configured as an input capture has the corresponding Data
Direction Register bit controlling the I/O direction of the associated pin.
MC9S12XHZ512 Data Sheet, Rev. 1.06
108
Freescale Semiconductor