S912XHZ512F1VAG Datasheet, PDF (111/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 2 Port Integration Module (S12XHZPIMV1)
Table 2-47. PPST Field Descriptions
Field
Description
7:0
Pull Select Port T
PPST[7:0] 0 A pull-up device is connected to the associated port T pin.
1 A pull-down device is connected to the associated port T pin.
2.3.11.7 Port T Wired-OR Mode Register (WOMT)
Module Base + 0x003B
7
R
WOMT7
W
6
WOMT6
5
WOMT5
4
WOMT4
3
2
1
0
0
MODRR2 MODRR1 MODRR0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 2-64. Port T Wired-OR Mode Register (WOMT)
Read: Anytime. Write: Anytime.
This register selects whether a port T output is configured as push-pull or wired-or. When a Wired-OR
Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a
high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured
as an input.
If IIC is enabled, the pins are configured as wired-or and the corresponding Wired-OR Mode Register bits
have no effect.
This register also configures the re-routing of IIC0, IIC1 and SCI1 on alternative ports.
Table 2-48. WOMT Field Descriptions
Field
Description
7:4
Wired-OR Mode Port T
WOMT[7:4] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
2
SCI1 Routing Bit — See Table 2-49..
MODRR2
1
IIC1 Routing Bit — See Table 2-50..
MODRR1
0
IIC0 Routing Bit — See Table 2-51..
MODRR0
Table 2-49. SCI1 Routing
MODRR[2]
0
TXD1
PP0
RXD1
PP2
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
111