|
S912XHZ512F1VAG Datasheet, PDF (403/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256 | |||
|
◁ |
Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description
9.3.2.16 ATD Conversion Result Registers (ATDDRx)
The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the
result registers bases on two criteria. First there is left and right justiï¬cation; this selection is made using
the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using
the DSGN control bit in ATDCTL5. Signed data is stored in 2âs complement format and only exists in left
justiï¬ed format. Signed data selected for right justiï¬ed format is ignored.
Read: Anytime
Write: Anytime in special mode, unimplemented in normal modes
9.3.2.16.1 Left Justiï¬ed Result Data
Module Base + 0x0010 = ATDDR0H
0x0012 = ATDDR1H
0x0014 = ATDDR2H
0x0016 = ATDDR3H
0x0018 = ATDDR4H
0x001A = ATDDR5H
0x001C = ATDDR6H
0x001E = ATDDR7H
0x0020 = ATDDR8H
0x0022 = ATDDR9H
0x0024 = ATDDR10H
0x0026 = ATDDR11H
0x0028 = ATDDR12H
0x002A = ATDDR13H
0x002C = ATDDR14H
0x002E = ATDDR15H
7
R (10-BIT) BIT 9 MSB
R (8-BIT) BIT 7 MSB
6
BIT 8
BIT 6
5
BIT 7
BIT 5
4
BIT 6
BIT 4
3
BIT 5
BIT 3
2
BIT 4
BIT 2
1
BIT 3
BIT 1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-18. Left Justiï¬ed, ATD Conversion Result Register x, High Byte (ATDDRxH)
0
BIT 2
BIT 0
0
Module Base + 0x0011 = ATDDR0L
0x0013 = ATDDR1L
0x0015 = ATDDR2L
0x0017 = ATDDR3L
0x0019 = ATDDR4L
0x001B = ATDDR5L
0x001D = ATDDR6L
0x001F = ATDDR7L
0x0021 = ATDDR8L
0x0023 = ATDDR9L
0x0025 = ATDDR10L
0x0027 = ATDDR11L
0x0029 = ATDDR12L
0x002B = ATDDR13L
0x002D = ATDDR14L
0x002F = ATDDR15L
7
6
5
4
3
2
1
0
R (10-BIT) BIT 1
BIT 0
0
0
0
0
0
0
R (8-BIT)
u
u
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 9-19. Left Justiï¬ed, ATD Conversion Result Register x, Low Byte (ATDDRxL)
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
403
|
▷ |