S912XHZ512F1VAG Datasheet, PDF (119/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

2.3.13.4 Port V Slew Rate Register (SRRV)
Chapter 2 Port Integration Module (S12XHZPIMV1)
Module Base + 0x0043
R
W
Reset
7
SRRV7
0
6
SRRV6
5
SRRV5
4
SRRV4
3
SRRV3
2
SRRV2
0
0
0
0
0
Figure 2-75. Port V Slew Rate Register (SRRV)
1
SRRV1
0
0
SRRV0
0
Read: anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PV[7:0].
Table 2-58. SRRV Field Descriptions
Field
Description
7:0
Slew Rate Port V
SRRV[7:0] 0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
2.3.13.5 Port V Pull Device Enable Register (PERV)
Module Base + 0x0044
7
R
PERV7
W
6
PERV6
5
PERV5
4
PERV4
3
PERV3
2
PERV2
1
PERV1
0
PERV0
Reset
0
0
0
0
0
0
0
0
Figure 2-76. Port V Pull Device Enable Register (PERV)
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 2-59. PERV Field Descriptions
Field
7:0
Pull Device Enable Port V
PERV[7:0] 0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Description
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
119