S912XHZ512F1VAG Datasheet, PDF (570/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 15 Serial Communication Interface (S12SCIV5)
15.3.2.4 SCI Alternative Control Register 1 (SCIACR1)
Module Base + 0x0001
7
6
5
4
3
2
1
R
0
0
0
0
0
RXEDGIE
BERRIE
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-7. SCI Alternative Control Register 1 (SCIACR1)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Table 15-7. SCIACR1 Field Descriptions
0
BKDIE
0
Field
Description
7
RSEDGIE
Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag,
RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
1
BERRIE
Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt
requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
0
BKDIE
Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt
requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled
MC9S12XHZ512 Data Sheet, Rev. 1.06
570
Freescale Semiconductor