S912XHZ512F1VAG Datasheet, PDF (137/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 3 512 Kbyte Flash Module (S12XFTX512K4V3)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x000C R
0
0
0
0
0
0
0
0
RESERVED1 _W
0x000D R
0
0
0
0
0
0
0
0
RESERVED2 _W
0x000E R
0
0
0
0
0
0
0
0
RESERVED3
W
0x000F
R
0
0
0
0
0
0
0
0
RESERVED4 _W
Figure 3-3. FTX512K4 Register Summary (continued)
3.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Module Base + 0x0000
R
W
Reset
7
FDIVLD
0
6
PRDIV8
5
FDIV5
4
FDIV4
3
FDIV3
2
FDIV2
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-4. Flash Clock Divider Register (FCLKDIV)
1
FDIV1
0
0
FDIV0
0
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
Table 3-2. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6
PRDIV8
5:0
FDIV[5:0]
Clock Divider Loaded.
0 Register has not been written.
1 Register has been written to since the last reset.
Enable Prescalar by 8.
0 The oscillator clock is directly fed into the clock divider.
1 The oscillator clock is divided by 8 before feeding into the clock divider.
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 3.4.1.1, “Writing the
FCLKDIV Register” for more information.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
137