S912XHZ512F1VAG Datasheet, PDF (527/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Table 14-18. CANIDAC Register Field Descriptions
Field
Description
5-4
Identifier Acceptance Mode — The CPU sets these flags to define the identifier acceptance filter organization
IDAM[1:0] (see Section 14.4.3, “Identifier Acceptance Filter”). Table 14-19 summarizes the different settings. In filter closed
mode, no message is accepted such that the foreground buffer is never reloaded.
2-0
Identifier Acceptance Hit Indicator — The MSCAN sets these flags to indicate an identifier acceptance hit (see
IDHIT[2:0] Section 14.4.3, “Identifier Acceptance Filter”). Table 14-20 summarizes the different settings.
IDAM1
0
0
1
1
Table 14-19. Identifier Acceptance Mode Settings
IDAM0
0
1
0
1
Identifier Acceptance Mode
Two 32-bit acceptance filters
Four 16-bit acceptance filters
Eight 8-bit acceptance filters
Filter closed
Table 14-20. Identifier Acceptance Hit Indication
IDHIT2
0
0
0
0
1
1
1
1
IDHIT1
0
0
1
1
0
0
1
1
IDHIT0
0
1
0
1
0
1
0
1
Identifier Acceptance Hit
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
Filter 4 hit
Filter 5 hit
Filter 6 hit
Filter 7 hit
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
14.3.2.13 MSCAN Reserved Register
This register is reserved for factory testing of the MSCAN module and is not available in normal system
operating modes.
MC9S12XHZ512 Data Sheet Rev. 1.06
Freescale Semiconductor
527