S912XHZ512F1VAG Datasheet, PDF (838/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 24 Interrupt (S12XINTV1)
24.3.1.2 XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Address: 0x0126
7
6
5
4
3
2
1
0
R
0
0
0
0
0
W
XILVL[2:0]
Reset
0
0
0
0
0
0
0
1
= Unimplemented or Reserved
Figure 24-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Read: Anytime
Write: Anytime
Table 24-3. INT_XGPRIO Field Descriptions
Field
Description
2–0
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the DMA interrupts
XILVL[2:0] coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Priority
low
high
Table 24-4. XGATE Interrupt Priority Levels
XILVL2
0
0
0
0
1
1
1
1
XILVL1
0
0
1
1
0
0
1
1
XILVL0
0
1
0
1
0
1
0
1
Meaning
Interrupt request is disabled
Priority level 1
Priority level 2
Priority level 3
Priority level 4
Priority level 5
Priority level 6
Priority level 7
MC9S12XHZ512 Data Sheet, Rev. 1.06
838
Freescale Semiconductor