S912XHZ512F1VAG Datasheet, PDF (387/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 9 Analog-to-Digital Converter (ATD10B16CV4) Block Description
9.3.2.4 ATD Control Register 3 (ATDCTL3)
This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze
Mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
Module Base + 0x0003
7
R
0
W
6
S8C
5
S4C
4
S2C
3
S1C
2
FIFO
Reset
0
0
1
0
0
0
= Unimplemented or Reserved
Figure 9-6. ATD Control Register 3 (ATDCTL3)
Read: Anytime
Write: Anytime
Table 9-8. ATDCTL3 Field Descriptions
1
FRZ1
0
0
FRZ0
0
Field
6
S8C
5
S4C
4
S2C
3
S1C
Description
Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 9-9 shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 9-9 shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 9-9 shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
Conversion Sequence Length — This bit controls the number of conversions per sequence. Table 9-9 shows
all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12
Family.
MC9S12XHZ512 Data Sheet, Rev. 1.06
Freescale Semiconductor
387