S912XHZ512F1VAG Datasheet, PDF (778/978 Pages) Freescale Semiconductor, Inc – Covers MC9S12XHZ384, MC9S12XHZ256

Chapter 22 S12X Debug (S12XDBGV3) Module
Table 22-23. State1 Sequencer Next State Selection (continued)
SC[3:0]
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Match2 triggers to State3....... Other matches have no effect
Match2 triggers to Final State....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect
Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
The trigger priorities described in Table 22-42 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
22.3.2.7.2 Debug State Control Register 2 (DBGSCR2)
Address: 0x0027
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
Figure 22-10. Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 22-1 and described in Section 22.3.2.8.1”. Comparators must be
enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Field
3–0
SC[3:0]
Table 22-24. DBGSCR2 Field Descriptions
Description
These bits select the targeted next state whilst in State2, based upon the match event.
SC[3:0]
0000
0001
Table 22-25. State2 —Sequencer Next State Selection
Description
Any match triggers to state1
Any match triggers to state3
MC9S12XHZ512 Data Sheet, Rev. 1.06
778
Freescale Semiconductor